Note ‒ A schematic is a communication tool; clarity outweighs artistic flair. Keep current flow left-to-right and signal flow top-to-bottom.

1. Symbols & Pins – Adopt IEEE/IEC symbols. Orient op-amp triangles ► pointing right; keep non-inverting (+) at top.
2. Power Rails – Label +VCC, -VEE, and use different ground symbols for analogue (AGND) and digital (DGND) returns to minimise noise coupling.
3. Junctions vs Cross-overs – Filled dot ● for an electrical junction; jumping arc ⤻ or “no-dot” cross for wires that merely pass.
4. Net Labels – Name critical nodes (VREF, SENSOR_IN, ADC_DRV) to reduce clutter and assist PCB layout.
5. Reference Designators – Resistor R1, capacitor C2, op-amp U1A; keep numbers sequential along signal path.

Tip ‒ Place decoupling capacitors (0 .1 µF + 10 µF) close to every IC power pin pair; draw them beside the IC for emphasis.

1. Voltage Divider – scales a high input to a lower measurable level.
   Formula: VOUT=VIN·R₂/(R₁+R₂)
2. Unity-Gain Buffer – an op-amp wired as a voltage follower isolates a sensor (high Z) from an ADC (low Z). Image 1 in the carousel shows the classic configuration.
3. RC Low-Pass Filter – suppresses HF noise before sampling.
   Cut-off: fc=1/(2πRC)
4. Non-Inverting Amplifier – boosts millivolt-level signals while preserving phase.
   Gain: AV=1+RF/RG
5. Instrumentation Amplifier – three-op-amp topology (Image 2) rejects common-mode noise; ideal for bridge sensors. Typical gain: AV=1+2R/RG (outer resistors matched).
6. Level Shifter – adds a DC offset so that a unipolar ADC can sample bipolar signals. Common practice: cascade divider → buffer → summer with reference.
7. Isolation & Protection – series R + TVS diodes for ESD, RC snubbers for inductive kick-back, and opto-isolators for high-side sensing.

Design Hint ‒ Always place your anti-alias RC filter after the buffer. The op-amp’s low output impedance ensures the calculated fc remains accurate.

Concept	Expression	Purpose
Ohm’s Law	V = I · R	Relate current, voltage & resistance.
Voltage Divider	VOUT=VIN·R₂/(R₁+R₂)	Attenuate or sense voltage levels.
Low-Pass RC Cut-off	fc=1/(2πRC)	Set anti-alias bandwidth.
Non-Inv Op-Amp Gain	AV=1+RF/RG	Amplify sensor outputs.
RC Time Constant	τ = R · C	Step response & settling time.
Impedance Match	ZOUT ≪ ZIN	Minimise loading error.

Derivation snap-in – For a first-order filter, the -3 dB point occurs where the magnitude of the transfer function drops to 1/√2. Starting from |H(jω)| = 1/√(1+(ωRC)²), set |H|=1/√2 ⇒ ω = 1/RC ⇒ fc=1/(2πRC).

1. Sense – RTH forms upper leg of a divider, R₁=10 kΩ to GND; mid-node scales 0 → 3.3 V.
2. Buffer – An OPA350 unity follower (Image 1) isolates the divider.
3. Filter – R=1 kΩ, C=4.7 nF gives fc≈34 kHz; enough beyond Nyquist of 4 kHz sample rate.
4. Level Shift – Not required (unipolar signal), so buffer drives ADC input directly.
5. ADC Drive – Add 47 Ω series resistor + 100 pF to meet datasheet RC<50 ns requirement.

; Minimal SPICE netlist for simulation
V1 VIN 0 DC 3.3
R1 VIN NODE1 10k
RTH NODE1 0 NTC10k
EBUF NODE2 0 NODE1 0 1   ; ideal op-amp buffer
RFLT NODE2 NODE3 1k
CFLT NODE3 0 4.7n
RLOAD NODE3 0 100k
.END

1. Schematic CAD – KiCad (free, hierarchical sheets) or Altium (rigid-flex, harness view).
2. Simulation – LTspice for linear circuits; add behavioural sources to model ADC sampling caps.
3. Revision Control – Store .sch/.pcb in Git with XML diffs enabled; commit netlist & BOM for CI-generated PDFs.
4. Design Reviews – Print schematics B/W, annotate reference currents, noise budgets, and dominant RC poles.
5. Documentation – Export annotated PDF with clickable net labels and embed the carousel images for quick visual context.

Further Reading – Texas Instruments “Analog Engineer’s Pocket Reference” and Analog Devices “Op-Amp Applications Handbook”.